Both approaches are viable, depending on what you want the synthesized implementation to be.
The indexed version would typically be used if you want the memory to be implemented using the internal block ram in the target device. In this case, the clock speed is limited by the memory access time.
The shift register version will use the registers in the logic cells, or in the case of Xilinx could use the SRL shift register mode of the LUTs. The shift register mode could potentially be faster, but it will use more routing and LUT resources.
In any case, you can always directly instantiate FPGA specific logic blocks in order to remove any ambiguity about how things get synthesized. The "generate custom IP" functions of FPGA development environments allow you to generate custom sized memories, FIFOs, shift registers, etc.